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BooherR. ., Division apparatus, . , . 235-167, 3222505.

BooherR. ., Multiplication apparatus, . , . 235--167, 3237000.

BooherR. -, Carry assimilating system, . , . 235-175, 3249747.

Borne J., Ribes M., Perfectionnements aux machines arithmetiques calculant des racines carrees, . ., . G06f, 1387911.

i I., laquo;Ideally fast raquo; decimal counters with bistables, laquo; Trans. Electron. Comput. raquo;, 1965, 14, 5, . 733-737.

r e 11 M., S h i f f A., Overflow indicator . . . 235-153, 3016193.

. , Universal radix adder., . , . 235-169, 3159740.

BrownN., Improvements relating to paraller digital adders, . ., . G4 A (G06f), 1040241.

BrownT. G., Jr , Self checking digital computer system, . , . 340-146, I, 3098994.

u e 1 w . ., i 1 s e n a t h ., Full adder, . , . 235-172, 3248529.

a 1 1 W. N. et al.. Transfer circuit for controlling data transfer from adder to accumulator, . , . 307-885, 3152262.

a 1 W. N., Pulse train sensing circuitry, . , . 235-164, 3157780.

Carrol W. N.. T i 1 t n . J., Asynchronous division apparatus, . , . 235-164, 3064896.

ChaoS. , High speed encoding with resistor-transistor logic circuits, laquo;Electronics raquo;, 1962, 35, N 6, . 48-51.

h i a p u z i A., Jr., Digital comparator, . , . 235-177, 3137789.

i f a i e 1 1 M., F e r r a r i D., Un circuito per la determi-nazione rapida dellordine di grandezza di un numero binario laquo;Alta frequenza raquo;, 1967, 36, N 6, . 565-568.

1 a r G. A., L a n g C. A., A new counting method for performing digital arithmetic, sElectron. Eng raquo;, 1963, 35, N 428, . 670-675, 703, 710.

a t e s . L., L e w i s P. M., II. Bistable device employing threshold gate circuits, . , . 307-88. 5, 3275849.

h a n L. L. et al., Fast multiply system, . , . 235-164, 3192366.

Cochrane . W., Binary matrix multiplier utilizing coincident inputs and sequential readout, . , . 235-164, 3104317.

Cochrane . W., Core matrix coded decimal parallel adder utilizing propagated carries, . , . 235-175, 3166669.

Computer arithmetic - 1 (Sympos. Summary), laquo;Proc. IFIP CADngr., New York City, 1965, vol. 2 raquo;, Washington, D. C, Spartan Books, 1966, . 440-446.



ConnetJ., Improvements relating to digital computers . ., . 106 (1), 909441.

n r E. D., Data timed mutiplication system, . , . 235-164, 3242304. .

Cooke-Ya borough E. ., Serial adder for bits occuiing in reverse time sequence, laquo;lnst. Elec. Ingrs-Electronic Letters* 1967 3, N 2, . 77-78.

Coop per R. A., Parallel adder, . , . 235-175. 3031140.

m 1 e i g h R. G., Serial binary adder, . , . 235-176, 3264458.

J. .. Electronic multiplier for variable field length computer, . , . 235-160, 3161764.

D a d d a L., Some schemes for parallel multipliers, laquo;Alta frequen-za raquo;, 1965, 34, N 5, . 349-356.

D a 1 W. G., KruyJ. F., A high speed arithmetic unit using tunnel diodes, laquo;1 Trans. Electron. Comput. raquo;, 1963, 12, N 5, . 503-511.

D a V i s . M., D e V e e r J. A., Divider utilising multiples of a divisor, . , . 235-156, 3234366.

D a V i s R. A., A checking arithmetic unit, laquo;AFIPS Conf. Proc. vol. 27, Part. 1 raquo;, Washigton D. C, Spartan Books, 1965, . 705-713.

DeerfieldA. J., Fast multiply apparatus, . , . 2.35-164. 3159739.

D e R eg t M. P., Negative radix arithmetic. Part 1. Introduction to negative radix number systems, laquo;Comput. Design*, 1967, 6, N 5, . 52-55, 57, 60, 62, 63.

Dickinson A. H., Electronic multipliers, . , . 235-160, 3015442.

Digital integrated micro circuits, their characteristic, prices and sources, laquo;Electronic Products raquo;, 1965, 7, N 8. . 87-103.

Dunv/ell S. W. etal.. Electronic calculator, . , . 340-172. 5, 3202969.

E a n s h a w J. ., FenwickP. M., Design for a parallel binary adder. .(Electron. Eng raquo;, 1966. 38, N 466, . 794-796, 831, 838.

Electronic multiplier hints use of modular arithmetic in computers Electronic Desing raquo;, 1963, v 11, N 19, . 12.

E 1 m r e W. ., M i n wr M., Arithmetic device, . , . 235-92, 2995298.

Emmons D. L., High speed comparator, . , . 340-146. 2, 3237159.

E i s n G. J., Segmented arithmetic device, . , . 235-164, 3234370.

Flo res J., The logic of computer arithmetic, London, Prentice-Hall, Int., 1963. , ,

Ferrari D., A. division method using a parallel multiplier, filEEETrans. Electron. Comput. raquo;. 1967, 16, N 2, . 224-226. , Fe rr i s A. L., Full adder, . , . 235- 76, 2998918.



Fialkowski ., Pseudosystematyczne zapisy dwojkowe, laquo;Arch. electrotechn. raquo;, 1965, 14, N 3, . 617-626.

F i s h 1 e r M. A., P e E. A., Threshold realization of arithmetic circuits, laquo;IRE Tran. Electronic Comput. raquo;, 1962, H, N 2, . 287-288.

F 1 n n M. J., L w P. R., The IBM System 360 Model 91. Some remarks on system development, laquo;IBM J. Res. and Developm raquo;, 1967, 11, N 1, . 2-7.

G 1 d b e r g J., Antiparallel control logic, laquo;1 Trans. Electron. Comput. raquo;, 1965,14, N 3, . 383-393.

Gottschalk H., Electronische Bausteinsysteme der Digital-technik, Berlin, Technik, 1965, . 68.

Gregory R. ., On the design of the arithmetic unit of a fixed-word-length computer from the standpoint of computational accuracy, laquo;1 Trans. Electron. Comput. raquo;, 1966, 15 N 2, . 255-257.

Grondbeginselen van het elekronisch tellen en de daarvoor benodig-de schakelingen. Vooral voor gecompliceerde apparaten verdienen synchrone tellers de voorkeur, laquo;Electronica raquo;, 1967, 20, N 490, . 438-443.

Hamming R. W., M a m m e 1 W. L., A note on the location of the binary point in a computing machine, laquo;1 Trans. Electron. Comput. raquo;, 1965, 14, N 2, . 260-261.

H a n d 1 e r W., Rechenwerk einer digitalen Rechenmaschine, . , . 42m, 24 (G06f), 1157009.

HarndenG. W., Estimating number of integrated circuits for systems, laquo;Electronic Products*, 1964, 7, N 7, . 30, 69.

H a d e n L. .. Tunnel diode majority logic serial binary adder/ substractor, . , . 235-172, 3260841.

e i j n . J., Binary parallel adder utilising sequential and simultaneous carry-generation, . , . 235-175, 3105897.

e 1 b i g W., W 1 d r i h R. J., High speed binary adder-substractor with carry ripple, . , . 235-175, 3198939.

Hendrickson . , Fast high-accuracy binary parallel addition, laquo;IRE Trans, on Electron. Comput. raquo;, 1960, vol EC-9, N 4, . 465-469.

H e n 1 e R. A., H i 1 1 L. L., Integrated computer circuits past, present and future, laquo;1 Proc. raquo;, 1966, 54, N 12, . 1849-1860.

Hertz T. M., YoungF. H., Binary square root mechanisation, . , . 235-158, 3049296.

e w d J. ., Arithmetic circuitry, . , . 235-170, 3112396.

b g G. G. et al.. Electronic adder using two decode counters alternately, . , . 235-176, 3161765.

m a n . ., 4-Megacycle 24-bit checked binary adder, laquo;1 Trans. raquo;, laquo;Communication and Electronic*, 1961, 80, part 1, N 56, . 443-450.

H t z G., Zweistufiges Rechenwerk, . , . 42m, 14 (G06f), 1184125.

Howe W. H., High speed logic circuit considerations, laquo;AFIPS Conf. Proc, 27, Part I raquo;, Washington, D. C, Spartan Books, 1965, p. 05-510.



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